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CD40174BMS
December 1992
CMOS Hex `D'-Type Flip-Flop
Pinout
CD40174BMS TOP VIEW
Features
* High Voltage Type (20V Rating) * 5V, 10V and 15V Parametric Ratings * Standardized, Symmetrical Output Characteristics * 100% Tested for Quiescent Current at 20V * Maximum Input Current of 1A at 18V Over Full Package Temperature Range, 100nA at 18V and +25oC * Noise Margin (Over full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of `B' Series CMOS Devices"
CLEAR 1 Q1 2 D1 3 D2 4 Q2 5 D3 6 Q3 7 VSS 8
16 VDD 15 Q6 14 D6 13 D5 12 Q5 11 D4 10 Q4 9 CLOCK
Applications
* Shift Registers * Buffer/Storage Registers * Pattern Generators
Functional Diagram
D1 3 F/F1 2 Q1
Description
CD40174BMS consists of six identical `D'-Type flip-flops having independent DATA inputs. The CLOCK and CLEAR inputs are common to all six units. Data is transferred to the Q outputs on the positive going transition of the clock pulse. All six flip-flops are simultaneously reset by a low level on the CLEAR input. The CD40174BMS is supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1E H6W
D2
4 F/F2
5
Q2
D3
6 F/F3
7
Q3
D4
11 F/F4
10
Q4
D5
13 F/F5
12
Q5
D5 CLOCK CLEAR
14 9 1 VSS = 8 VDD = 16 F/F6
15
Q6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3359
7-1384
Specifications CD40174BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL5 VIH5 VIL15 VIH15 VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25 C +125
oC o
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 -
MAX 2 200 2 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
-55o
C
+25 C +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC -55oC -55oC
o
14.95 0.53 1.4 3.5 -2.8 0.7
VOH > VOL < VDD/2 VDD/2
3.5 11
1.5 4 -
V V V V
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-1385
Specifications CD40174BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH FCL VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN 3.5 3.5/1.35 MAX 300 405 200 270 200 270 UNITS ns ns ns ns ns ns MHz MHz
PARAMETER Propagation Delay Clock to Output Propagation Delay CLEAR to Output Transition Time
SYMBOL TPHL1 TPLH1 TPHL2
CONDITIONS (Note 1, 2) VDD = 5V, VIN = VDD or GND
+25oC +125oC, -55oC
+25oC +125oC, -55oC
Maximum Clock Input Frequency NOTES:
+25oC +125oC, -55oC
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 MAX 1 30 2 60 2 120 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA
+125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC
+125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC
+125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5B VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC
7-1386
Specifications CD40174BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH15 CONDITIONS VDD =15V, VOUT = 13.5V NOTES 1, 2 TEMPERATURE +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay Clock to Output Propagation Delay CLEAR to Output Transition Time VIL VIH TPHL1 TPLH1 TPHL2 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TTHL TTLH FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V TS VDD = 5V VDD = 10V VDD = 15V Minimum Data Hold Time TH VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Maximum Clock Rise and Fall Time TRCL TFCL VDD = 5V VDD = 10V VDD = 15V Minimum CLEAR Removal Time TREM VDD = 5V VDD = 10V VDD = 15V Minimum CLEAR Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance CIN CLEAR All others NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25 C +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
o
MIN +7 6 8 15 15 15 -
MAX -2.4 -4.2 3 140 100 100 80 100 80 40 20 10 80 40 30 130 60 40 0 0 0 100 50 40 40 7.5
UNITS mA mA V V ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns s s s ns ns ns ns ns ns pF pF
Maximum Clock Input Frequency Minimum Data Setup Time
7-1387
Specifications CD40174BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 7.5 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-1 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 0.2A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
7-1388
Specifications CD40174BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 (Note 1) Static Burn-In 2 (Note 1) Dynamic Burn-In (Note 1) Irradiation (Note 2) NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN GROUND VDD 16 1, 3, 4, 6, 9, 11, 13, 14, 16 1, 16 1, 3, 4, 6, 9, 11, 13, 14, 16 2, 5, 7, 10, 12, 15 9 3, 4, 6, 11, 13, 14 9V -0.5V 50kHz 25kHz
2, 5, 7, 10, 12, 15 1, 3, 4, 6, 8, 9, 11, 13, 14 2, 5, 7, 10, 12, 15 2, 5, 7, 10, 12, 15 8 8 8
Logic Diagram
CL p D n 3 (4, 6, 11, 13, 14) CL CL p n CL CLR* 1 CL CLK* 9 CL * All inputs (terms 1, 3, 4, 6, 9, 11, 13, 14) protected by COS/MOS protection network n CL CL p n CL VSS 2 (5, 7, 10, 12, 15) CL p Q VDD
FIGURE 1. 1 OF 6 FLIP-FLOPS TRUTH TABLE FOR 1 OF 6 FLIP-FLOPS INPUTS CLOCK DATA 0 1 X X
1 = High Level 2 = Low Level
OUTPUT CLEAR 1 1 1 0
X = Don't Care NC = No Change
Q 0 1 NC 0
X
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
1389
CD40174BMS Typical Performance Curves
OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (fTHL, fTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
200 SUPPLY VOLTAGE (VDD) = 5V
150
100 10V 50 15V
10V
5V 0 5 10 15
0 0
20
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
AMBIENT TEMPERATURE (TA) = +25oC
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
0
0 -5 -10 -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 10V
-10V
-20 -25
-15V 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-30
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
POWER DISSIPATION PER FLIP-FLOP (PD) (W) 105
8 6 4 2
0
AMBIENT TEMPERATURE (TA) = +25oC
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
104
SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V
8 6 4 2
103
-10V
-10
8 6 4 2
102
-15V
-15
8 6 4 2
CL = 50pF CL = 15pF
10 1
2
4
10 103 102 CLOCK INPUT FREQUENCY (fCL) (kHz)
68
2
4
68
2
4
68
2
4
68
104
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY
7-1390
CD40174BMS Typical Performance Curves
PROPAGATION DELAY TIME (tPHL, tPLH) (ns) 200 AMBIENT TEMPERATURE (TA) = +25oC 175 SUPPLY VOLTAGE (VDD) = 5V 150 125 100 10V 75 15V 50 25 0
(Continued)
0
10
20
30
40
50
60
70
80
90
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME (CLOCK TO OUTPUT) AS A FUNCTION OF LOAD CAPACITANCE
Waveform
Pad Layout
tr CL CLOCK INPUT tH(HL)* DATA INPUT tSU(LH)* tTLH OUTPUT tPLH tREM 50%
tf CL
VDD 90% 50% 10% tH(LH)* VDD 50% 0 VDD 90% 50% 10%
0
tSU(HL)* tTHL
0
tPHL *(LH) OR (HL) OPTIONAL
VDD CLEAR 0
FIGURE 9. DEFINITION OF SETUP, HOLD, PROPAGATION DELAY, AND REMOVAL TIMES
DIMENSIONS AND PAD LAYOUT FOR CD40174BMSH
The photographs and dimensions of each CMOS chip represent a chip when it is part of the wafer. When the wafer is separated into individual chips, the angle of cleavage may vary with respect to the chip face for different chips. The actual dimensions of the isolated chip, therefore, may differ slightly from the nominal dimensions shown. The user should consider a tolerance of -3 mils to +16 mils applicable to the nominal dimensions shown. Dimension in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: PASSIVATION: BOND PADS:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1391

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